The present invention relates to sigma-delta Analog-to-Digital Converters (ADCs), and, more particularly, to a sigma-delta ADC having efficient dithering.
Most sigma-delta modulators include periodic idle channel noise. Even after lowpass filtering, the peak amplitudes of the periodic idle channel noise can be relatively high, even though the RMS power level of the noise is low. Accordingly, this noise gives rise to an annoying sound for the human ear in any audio application; yet, this same idle channel noise may not interfere with a data acquisition system using the same modulator.
An example of a second-order sigma-delta modulator architecture susceptible to having idle channel noise is shown in FIG. 1. As shown, modulator 10 includes two integrators, 16 and 22, and two negative feedback loops, wherein the first feedback loop includes a digital-to-analog converter (DAC) 26. Summers, 12 and 20, couple these two negative feedback loops to the feed forward portion of modulator 10. Coefficients k1 and k2 supplied by respective multipliers, 14 and 18, represent forwarding coefficients, while coefficients kf1 and kf2 supplied by respective multipliers, 28 and 30, represent feedback coefficients. Quantizer 24 can be a two-level quantizer having one bit or a multi-level quantizer having three or more bits. When the input x(n) is a small DC signal or some small DC offset and the channel is idle, the output y(n) of the sigma-delta modulator will exhibit a series of digital codes having a low frequency pattern proportional to the DC offset and the sampling clock. As explained previously, in audio applications where there is a DC offset in addition to a small frequency signal, the idle channel tones could lead to an unpleasant sound.
Conventional dithering methods to whiten or decorrelate the idle channel tones include but are not limited to, (1) adding an out-of-band sine or square wave; (2) adding a DC offset to the input of the modulator; (3) adding a small amount of white noise to the input; (4) adding a small-amplitude periodic pulse train; and (5) starting the integrators with irrational values. These techniques are either too complicated to implement or are not effective.
An effective dithering method is to add dither in such a way that the dither transfer function is the same as the quantization noise transfer function. This generalized dither is shown in FIG. 2a. As shown, input x(n) represents the input signal that is fed to a feed forward Z transfer function G(z) 104. Through summer 106, a dither input d(n) is added to the resultant signal of the feed forward Z transfer function G(z) 104. Quantizer 108 receives the result to provide an output y(n). Output y(n) is fed back through a feedback transfer function H(z) 112 and the output of transfer function H(z) 112 is added to the input using summer 102. An error function e(n) is provided through the subtraction of the signal after summer 106 from the output signal y(n).
In the alternative, as shown in FIG. 2b, the dither input d(n) can be added to the input of quantizer 120 directly or added to the input of modulator 120 after a pre-filter 122. As shown, the input x(n) is summed with the output of the pre-filter 122 using adder 124. The feed forward Z transfer function G(z) couples to receive sum and provides its result to quantizer 128. The output y(n) is fed back to feedback transfer function H(z)132. Adder 124 sums the result to feed forward portion of modulator 120. Adding dither to the input of the quantizer is not simple. An equivalent representation is to shift the decision thresholds of the quantizer.
Conventionally a uniformly distributed signal is added in front of the quantizer so that the x and y signals maintain the same transfer function. Given the hypothetical when an input signal is fixed having a small DC offset, the idle channel tone can repeat itself for several cycles; thereby creating a periodic idle channel tone. When, however, a dithering sequence is added, the periodic idle channel tone is destroyed. Thus, the resultant signal will look more like a random signal where the power is reduced and spread over the frequencies.
In general, an idle channel tone is proportional to the input DC offset. Thus, if there is a fixed DC offset there is a fixed frequency. Once, however, dithering is introduced, the output will a decreased power for that fixed frequency and the other frequencies may increase in power.
FIG. 3 illustrates a known method and apparatus for adding a dither signal to a 3-level quantizer. Specifically, FIG. 3 gives the details of how the dithering signal may couple into the quantizer 108 as shown in FIG. 2a. The input signal Vin comes from the feed forward Z transfer function G(z) as is shown in FIG. 2a. Conventionally, the first threshold voltage Vth0 is the negative value of the second threshold voltage Vth1 where Vth0=xe2x88x92-Vth, Vth1=Vth. The first and second threshold voltages, Vth0 and Vth1, are received by the inverted input of each comparator, 136 and 134, respectively. Signals B0 and B1, represent the output signal y(n) of FIG. 2a. As shown, adder 132 adds a pseudo-random series dither d(n) to the quantizer input represented by Vin, wherein the quantizer is implemented using adder 132 and comparators, 134 and 136. When the inputs (Vin+d(n)) of comparators, 134 and 136, are larger than threshold voltage Vth, the output nodes B1B0 are both high or xe2x80x9c11xe2x80x9d. As shown in FIG. 2, when the digital signal y(n) is fed back to the transfer function H(z), it is converted to an analog signal proportional to a reference voltage Vref. This reference voltage Vref is fed back to the integrators coupled as shown in FIGS. 1 and 2. When the inputs (Vin+d(n)) of comparators, 134 and 136, are less than or equal to threshold voltage Vth and greater than the negative value of threshold voltage xe2x88x92Vth, the output nodes B1B0 are both low or xe2x80x9c00xe2x80x9d. Thereby a value of xe2x80x9c0xe2x80x9d is fed back to the integrators. When the input (Vin+d(n)) of the comparators, 134 and 136, are less than the negative value of threshold voltage xe2x88x92Vth the output nodes B1B0 are both high or xe2x80x9c11xe2x80x9d. As a result, the negative value of reference voltage xe2x88x92Vref is fed back to the integrators. The 0 dBFS input to the converter, in this case is the transfer function H(z), is either a positive or negative value of the reference voltage +/xe2x88x92Vref .
Without a dither signal where d(n)=0 for all n, the decision threshold window for the quantizer is (xe2x88x92Vth, Vth). With the dither signal d(n), the window is shifted to (xe2x88x92Vthxe2x88x92d(n), Vthxe2x88x92d(n)). When the dither signal d(n) is a pseudorandom series, the window shifts randomly and, thereby, generates a decorrelated output sequence. Thus, the periodicity of the output series y(n) is destroyed and the idle channel tones are removed.
The dithering d(n) amplitude, however, must be large enough to remove the idle channel tones. For example, for a 1-bit quantizer, the ratio of the peak-to-peak range of the dither to the quantizer interval xcex4/xcex94 must be greater than 0.5, where xcex4 is the peak-to-peak range of the dither and xcex94 is the quantizer interval. The dynamic range is degraded by 5 dB when dither peak-to-peak range xcex4 is equal to quantizer interval xcex94.
For a high input signal range, however, there still exists penalties wherein the signal to noise ratio decreases when there is a high input signal. Thus, a need exists for a more efficient dithering method that removes idle channel noise from a sigma-delta modulator.
To address the above-discussed deficiencies of sigma-delta modulators, the present invention teaches a sigma-delta modulator having a more efficient dithering method that removes idle channel noise. This sigma-delta modulator and novel dithering method for removing the idle channel tones of sigma-delta analog-to-digital converters (ADC) includes adding dither by stretching the threshold windows randomly. The randomly stretched window destructs the periodicity of sigma-delta ADC modulator""s output sequence and, thereby, removes the idle channel tones.
The sigma-delta modulator in accordance with the present invention includes a first adder, a feed forward transfer function G(z), a quantizer circuit and a feed back transfer function H(z). The quantizer circuit includes a second adder, a first dither signal generator, a first comparator, a third adder, a second dither signal generator, and a second comparator. The second adder receives the first threshold and adds the dither signal provided by the first dither signal generator to this first threshold. The first comparator compares the input signal with the sum generated by the second adder. The third adder receives the second threshold and subtracts the second dither signal generated by the second dither signal generator from the second threshold. The second comparator compares the input signal with the result generated by the third adder.
The sigma-delta modulator in accordance with the present invention does not necessarily have to be one of a first order. It may be comprised more than one stage.
Advantages of this design include but are not limited to sigma-delta modulator having a more efficient dithering method that removes idle channel noise from a sigma-delta modulator. Compared to conventional dithering techniques that add random noise to the input of the quantizer, this novel dithering technique and apparatus has a higher allowed input dynamic range and higher signal-to-noise-plus-distortion-ratio (SNDR).
These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings.